1. Field of the Invention
The invention relates in general to a method for manufacturing a polysilicon layer and a thin film transistor (TFT) using the same, and more particularly to a method of completely melting an amorphous silicon layer to laterally grow into a polysilicon layer and a thin film transistor (TFT) using the same.
2. Description of the Related Art
With advanced development of technology, flat display panels have been popularly applied to various portable electrical devices, such as notebook computers, personal digital assistants (PDAs), and cellular phones. Normally, flat display panels can be divided into amorphous silicon thin film transistor (a-Si TFT) display panels and low temperature polysilicon (LTPS) TFT display panels. The difference is that the amorphous silicon layer is transformed into a polysilicon layer in LTPS panels. Therefore, driving circuits and integrated circuits (ICs) can be integrated onto LTPS TFT panels with promoted electron mobility to provide highly freedom of nimble design in panels and circuits.
Referring to FIG. 1A to FIG. 1D, the cross-sectional views show a manufacturing flow of a conventional method for a polysilicon layer disclosed on TW Patent 452892. At first, a substrate 11 is provided and an insulating layer 40 is formed on the substrate 11, as shown in FIG. 1A. Next, an amorphous silicon layer 13 is formed on the insulating layer 40. The amorphous silicon layer 13 includes at lease one first region 13a and a second region 13b, and the thickness of the first region 13a is greater than that of the second region 13b, as shown in FIG. 1B. Then, the second region 13b of the amorphous silicon layer 13 is completely melted while the first region 13a of the amorphous silicon layer 13 is partly-melted by using an excimer laser 50 to form a melted amorphous silicon layer 60 on the residue of the first region 13a, as shown in FIG. 1C. The melted amorphous silicon layer 60 includes at least one first melted region 60a and one second melted region 60b. The melted amorphous silicon layer 60 has a temperature gradient because the temperature T4 of the center D1 of the first melted region 60a is less than the temperature T5 of the center D2 of the second melted region 60b. Further, the residue of the first region 13a is used as seed to perform re-crystallization. According to the directions of the temperature gradient in FIG. 1C, the melted amorphous silicon layer 60 is crystallized to form a polysilicon layer 14, as shown in FIG. 1D. The crystallization begins form the first melted region 60a to the second melted region 60b along the arrow in FIG. 1C.
Since the first region 13a of the amorphous silicon layer 13 is partly-melted, the melted amorphous silicon layer 60 processes lateral growth by using the residue of the first region 13a as seed so that the less grain size with respect to the first region 13a in the polysilicon layer 14 is obtained. As the result, only the region with respect to the second region 13b in the polysilicon layer 14 can be used to be channel regions of electrical devices, such as the polysilicon channel regions of a LTPS TFT, source and drain of which is with respect to the first region 13a of the amorphous silicon layer 13. However, because a grain boundary and the residue of the first region 13a are on the channel regions of the polysilicon layer 14 with respect to the second region 13b, the electron mobility of electrical devices is diminished and the electrical property of LTPS TFT is greatly influenced.